programmable divider
英 [ˈprəʊɡræməbl dɪˈvaɪdə(r)]
美 [ˈproʊɡræməbl dɪˈvaɪdər]
网络 可编程分频电路; 可编程分频器
双语例句
- Design of novel programmable divider with high speed and low noise
新型高速低噪声可编程分频器的设计 - A programmable multi-modulus frequency divider is designed and implemented in a0.
多模基带处理器是一种兼容多标准的通信平台。 - Design of a Wide Dividing Range CMOS Programmable Divider
一种宽分频范围的CMOS可编程分频器设计 - In this paper, a wide range programmable divider based on dual-modulus prescaler is proposed.
设计了一种基于双模预分频的宽范围可编程分频器。 - The down scalers are comprised of dual modulus prescaler ( DMP) and programmable& pulse swallow divider, different methods of high frequency analog circuit and digital logical synthesis are adopted respectively.
采用了高速射频双模预分频器与数字逻辑综合生成的可编程吞脉冲分频器相结合的设计方法。 - Design of a High Speed Pulse Swallow Programmable Frequency Divider and Its PSPICE Simulation
高速吞脉冲程序分频器的电路设计与PSPICE模拟 - Design and Performance Test of Programmable Circuit in Programmable Control Voltage Divider
程控分压器程控电路的设计及性能测试 - Based on microcomputer, a design thought of PC's digital and Programmable frequency divider card is put forward and a design way of hardwares and softwares is set. The PC's digital and programmable frequency divider card is designed and accomplished by applying the thought and method.
本文以微型计算机为基础，提出了基于PC机的数字程控分频器卡的设计思想，阐述了硬件、软件设计的具体方法，应用这一思想和方法设计并实现了基于PC机的数字程控分频器卡。 - An improved programmable divider
一种改进的程序分频器 - A research and design of digital and programmable frequency divider card based on PC
基于PC机的数字程控分频器卡的研究与设计 - A high speed ECL programmable frequency divider is described in the paper. including the design of logic, circuit and layout as well as the temperature compensation considerations.
本文介绍了一种ECL高速可编程分频器的逻辑设计、电路设计、温度补偿设计、版图设计及研制结果。 - The logic and circuit design of a very high speed ECL programmable frequency divider is described.
介绍一种ECL高速程控分频器的逻辑设计、电路设计及研制结果。 - A programmable divider of frequency synthesizer applied to the 802.11b protocol is presented.
介绍了一种应用于802.11b的频率合成器中的可编程分频器。 - Design of Programmable Control n Frequency Divider Based on GAL Chip
基于GAL的可程控n分频器设计 - Therefore, we develop the programmable divider which use traditional Phase Lock Loop principle and the frequency synthesizer theory. We utilize the CPLD which is developed by Altera and make use of the VHDL to make the design of kernel programme.
为此，本文研制了程序分频器，它利用了传统锁相环路原理，以及频率合成器的理论，使用Altera公司开发的CPLD，同时使用VHDL硬件描述语言进行核心程序的设计。 - 0.18 μ m CMOS Programmable Frequency Divider for PLL-Based Frequency Synthesizer
0.18μmCMOSPLL频率综合器中可编程分频器的设计与实现 - A 600 MHz ECL Programmable Frequency Divider
一种600MHzECL高速程控分频器的设计 - Design on the Programmable Divider and Research on the Transcoding of MPEG Audio Bit-Stream
MPEG-2码流发送系统程序分频器的设计及MPEG音频码流转换编码技术研究 - Two operation modes ( integer/ fractional-N) are achieved by switching on/ off the output signal of ΣΔ modulator. Just a programmable counter is needed for the swallow pulse divider.
通过打开或者关断∑Δ调制器的输出来实现分数和整数分频两种工作模式，仅用一个可编程计数器实现吞脉冲分频器的功能。 - Programmable Precision Voltage Divider and its Application
可编程精密电压分压器及其应用 - And Key point is realization of the high quality double cross coupling VCO and programmable 2/ 3 divider in the high frequency.
重点研究了高性能双交叉耦合VCO实现和高频下可编程2/3分频器的电路实现。 - Only a programmable counter is needed for the swallow pulse divider.
吞脉冲分频器仅需要一个可编程计数器。 - Based on the CML divider, a programmable divider was implemented.
在这个CML分频器基础上，设计了一个可编程分频器。